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100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
entity test_decoder3 is
end test_decoder3;
architecture BENCH of test_decoder3 is
component decoder3
port(
Sel : Bit_vector ( 1 to 3 );
Do
100vhdl+
-- Author : yzf
-- Created On: Tue Dec 12 08:26:19 1995
-- Testbench for prefetch.prefetch
use work.types.all;
architecture BENCH of test_prefetch is
component prefetch
PORT(
BR
100vhdl+
-- Author : yzf
-- Created On: Tue Dec 12 08:26:19 1995
-- Testbench for prefetch.prefetch
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_prefetch is
end t
100vhdl+
--**VHDL*************************************************************
--
-- SRC-MODULE : PREFETCH
-- NAME : prefetch.vhdl
-- VERSION : 1.0
--
-- PURPOSE : Architecture of PREFETCH b
100vhdl+
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distribu
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity tb_decoder is
end tb_decoder;
architecture tb of tb_decoder is
component decoder
port(keypad:in std_logic