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找到约 10,000 项符合「VHDL」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/493788/6390677

cdf adsuart.cdf

/* Quartus II Version 4.1 Build 181 06/29/2004 SJ Full Version */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); P ActionCode(Cfg) Device PartName(EP1C3T144) Path("F:/XD_DSP/EDA_VHDL_E
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www.eeworm.com/read/493788/6390679

rpt adsuart.asm.rpt

Assembler report for ADSUART Mon Aug 01 14:30:17 2005 Version 4.1 Build 181 06/29/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice
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www.eeworm.com/read/493792/6390697

cdf color.cdf

/* Quartus II Version 4.1 Build 181 06/29/2004 SJ Full Version */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); P ActionCode(Cfg) Device PartName(EP1C3T144) Path("E:/EDA_VHDL_Expt3/Ch
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www.eeworm.com/read/493792/6390704

rpt color.asm.rpt

Assembler report for COLOR Tue May 10 15:13:25 2005 Version 4.1 Build 181 06/29/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2.
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www.eeworm.com/read/493793/6390946

cdf step_a.cdf

/* Quartus II Version 4.1 Build 181 06/29/2004 SJ Full Version */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); P ActionCode(Cfg) Device PartName(EP1C3T144) Path("F:/XD_DSP/EDA_VHDL_E
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www.eeworm.com/read/489750/6469258

txt caidengkongzi.txt

一、设计任务与要求 设计一个彩灯控制器，彩灯控制器的第1种花样为彩灯从右到左，然后从左到右逐次点亮，接着全灭全亮；第2种花样为彩灯两边同时亮1个，并逐次向中间移动再散开；第3种花样为彩灯两边同时亮2个逐次向中间移动再散开；第4种花样为彩灯两边同时亮3个，然后4亮4灭，4灭4亮，最后1灭1亮。4种花样自动变换，循环往复。 二、电路原理分析与方案设计 <mark>VHDL</mark>是美国国防部提出的一种经过标准化认证 ...
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www.eeworm.com/read/487908/6501807

txt readme.txt

注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化
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www.eeworm.com/read/487583/6505580

qsf clock.qsf

# Copyright (C) 1991-2008 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/487358/6509277

prj test_register_beh.prj

vhdl work "register_16bits.vhd" vhdl work "mux_16_to_1.vhd" vhdl work "demux_1_to_16.vhd" vhdl work "regisster_set.vhd" vhdl work "test_register.vhw"
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www.eeworm.com/read/487358/6509285

prj regisster_set_stx.prj

vhdl isim_temp "register_16bits.vhd" vhdl isim_temp "mux_16_to_1.vhd" vhdl isim_temp "demux_1_to_16.vhd" vhdl isim_temp "regisster_set.vhd"
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