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---------------------- PACKAGE bit_rtl_pkg is ---------------------- subtype short is integer range 0 to 65535; subtype int4 is integer range 0 to 16; subtype int8 is integer range 0

use work.bit_rtl_pkg.all; -------------------------------------- -- MUX2 -- 2 select 1 multiplexer -------------------------------------- entity bit_rtl_mux2 is port ( in1 : in bit_vector;

--**VHDL************************************************************* -- -- SRC-MODULE : TESTBENCH -- NAME : falsepath_stim.vhdl -- VERSION : 1.0 -- -- PURPOSE : Testbench for falsep

--**VHDL************************************************************* -- -- SRC-MODULE : FALSEPATH -- NAME : falsepath.vhdl -- VERSION : 1.0 -- -- PURPOSE : Architecture of FALSEPATH

-------------------------------------------------------------------------------- -- -- Controller Counter Benchmark -- Simulation Vectors -- -- Model Source: Chip Level modelling with VHDL by Ji

--*************************************************************************** -- pack.vhdl * -- VHDL BIT_VECTOR Ope

-------------------------------------------------------------------------------- -- -- Controlled Counter Benchmark -- -- Source: "Chip Level Modeling with VHDL" by Jim Armstrong (Prentice-Hall 19