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找到约 10,970 项符合 VHDL 的代码

clk_div3.prj

vhdl work clk_div3.vhd

coregen.log

# Xilinx CORE Generator 6.3i # User = xiaoshichang Initializing default project... Loading plug-ins... All runtime messages will be recorded in H:\金美通信1\vhdl程序\clk_div3\coregen.log NEWPROJECT .

getinstr.prj

vhdl work GetInstr.vhd

alu.prj

vhdl work alu.vhd

tcpu.udo

-- ProjNav VHDL simulation template: tcpu.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

cpu.prj

vhdl work timer.vhd vhdl work GetInstr.vhd vhdl work alu.vhd vhdl work exe.vhd vhdl work memcontrol.vhd vhdl work cpu.vhd

memcontrol.prj

vhdl work memcontrol.vhd

walu.udo

-- ProjNav VHDL simulation template: walu.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

tcpu1.udo

-- ProjNav VHDL simulation template: tcpu1.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

wexe.udo

-- ProjNav VHDL simulation template: wexe.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands