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library ieee; use ieee.std_logic_1164.all; --library bitlib; use work.bit_pack.all; entity static_ram is generic ( --下面给出的是RAM6116的时间特性值 --在本系统的组装中将被置为43258A-25CMOS RAM

package bit_pack is --功能是把bit_vector转换成整型 function vec2int(vec1:bit_vector) return integer; --功能是把integer转换为bit_vector类型 function int2vec(int1,Nbits:integer) return bit_vector

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library ieee; use ieee.std_logic_1164.all; entity tb_alarm_controller is end tb_alarm_controller; use work.p_alarm.all; architecture test of tb_alarm_controller is component alarm_controll

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entity gcd is port(start: in bit; clk : in bit; din : in bit; xi,yi: in integer; dout : out bit; output:out integer); end gcd; architecture behavior of gcd is begin process

library ieee; use ieee.std_logic_1164.all; entity gcd_tester is end gcd_tester; architecture test of gcd_tester is signal start:bit :='0'; signal clk:bit :='0'; signal din:bit :='0'; signa

-- Page : 278 - 278 -- -- Objective : wait until... -- -- File Name : test_3.vhd -- -- Author : Joseph Pick -- entity Test_3 is end Test_3; architecture Behave_1 of Test_3 is