代码搜索结果

-proj f:\aa -t test.tbw -source serial.vhdl -entity serial -ipcport 1156

vhdl work ctrl.vhdl

vhdl work xmit.vhdl

#-- Synplicity, Inc. #-- Version 6.0 #-- Project file D:\projects\altera\lpcores\ddr\release\VHDL\V1_0\synthesis\synplicity\ddr_sdram.prj #-- Written on Fri Jun 30 17:01:13 2000 #add_file opti

Synthesizing work.ddr_sdram.rtl @W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_sdram.vhd":131:14:131:16|Port direction mismatch between component and entity Synthesizing work.pll1.s

reg4.vhd，reg4_1.vhd,reg8.vhd,add4.gdf,add8.gdf 流水线加法器 mul_8.vhd，mul8.gdf 流水线乘法器 first.vhd,second.vhd 寄存器VHDL优化编码

cnt6,count60,counter60.vhd 计数器的图形和VHDL设计

-- ProjNav VHDL simulation template: TEST602.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

-- ProjNav VHDL simulation template: TEST60.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

vhdl work "Hour.vhf"