代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
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www.eeworm.com/read/208258/15250086
log coregen.log
# Xilinx CORE Generator 6.2i
# User = zsx
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\VHDL\JIAOTONG\coregen.log
# busformat=BusFormatAngleBrack
www.eeworm.com/read/208256/15250196
lfp yjiao.lfp
# begin LFP file F:\dragon\VHDL\myboard\lcd162\yjiao.lfp
designfile lcd162.ngd
IO_GROUP "d" ;
NET "d" IO_GROUP="d" ;
NET "d" IO_GROUP="d" ;
NET "d" IO_GROUP="d" ;
NET "d" IO_GROU
www.eeworm.com/read/207756/15262757
udo test.udo
-- ProjNav VHDL simulation template: test.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
www.eeworm.com/read/207756/15262797
udo lian.udo
-- ProjNav VHDL simulation template: lian.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
www.eeworm.com/read/168634/5441116
compilefordebussy
#!/bin/csh -f
if(-e work.lib++) then
\rm -rf work.lib++
endif
# /dq2/qa/Debussy/prod/4.4/Main/bin/vericom \
vericom \
-v ../verilog/src/mem.v \
../verilog/RTL/TopModule.v \
../verilog/RTL/ALUB.v
www.eeworm.com/read/168399/5447267
npl standalone.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT standalone
DESIGN standalone
DEVFAM virtex2p
DEVFAMTIME 0
DEVICE xc2vp30
DEVICETIME 0
DEVPKG ff896
DEVPKGTIME 0
DEVSPEED -7
DEVSPEEDTIM