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VHDL 的代码
100vhdl+
--***************************************************************
-- Following first two examples show that object of std_logic and
-- object of logic can be assigned to each other
-- Bbut
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
package logic_pack is
function resolve(s : std_ulogic_vector) return std_ulogic;
SUBTYPE logic is resolve std_ulogic;
TYPE logic_vector IS ARRAY
100vhdl+
package p is
attribute cycle_time:Time;
attribute max_cycles:Integer;
attribute clock_phases:Integer;
attribute Integer_width:Integer;
Type my_integer is range -2**15 to 2*
100vhdl+
--write by diao lan song
--1998/9/23
Use work.p.all;
ENTITY e_stim IS END e_stim ;
ARCHITECTURE stimulation OF e_stim IS
COMPONENT e_bus
port(bus1 : Inout wired_and my_intege
100vhdl+
package logic is
type Bit_vector is array (Natural range ) of Bit;
end logic;
use WORK.logic.all;
entity And2 is
port( I1,I2: Bit; O1: out Bit);
end and2;
architecture And2_archit of
100vhdl+
entity bit_rtl_reg_clk is
port (
pin : bit_vector;
cntl : bit;
clk : bit;
pout : out bit_vector
);
end bit_rtl_reg_clk;
architecture func of bit_rtl_reg_clk is
begin