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100vhdl+
--Page : 283
--Objective : Deadlock
--Filename : test_13a
--Author : Joseph Pick
entity Test_13a is
end Test_13a;
architecture Behave_1 of Test_13a is
signal A : NATURA
100vhdl+
--Page :308,309
--Objective :Function slices
--Filename :test_105.vhd
--Author :Joseph Pick
entity Test_105 is
end Test_105;
architecture Behave_1 of Test_
100vhdl+
-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
entity tb_fq_divider is
end tb_fq_divider;
architecture test of tb_fq_divider is
component fq_divider
port(
clk_in
100vhdl+
-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_BAND is
-----------------------------------------------------------
generic(
100vhdl+
entity bit_rtl_lt_nc is
port (
in1 : bit_vector;
in2 : bit_vector;
pout : out bit
);
end bit_rtl_lt_nc;
architecture func of bit_rtl_lt_nc is
begin
process(in1,in2)