代码搜索:VHDL

找到约 10,000 项符合「VHDL」的源代码

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www.eeworm.com/read/244009/7118118

rpt testfreq.map.rpt

Analysis & Synthesis report for testfreq Thu Aug 30 02:46:44 2007 Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version --------------------- ; Table of Contents ; ---------------------
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rpt testfreq.map.rpt

Analysis & Synthesis report for testfreq Thu Aug 23 10:01:09 2007 Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version --------------------- ; Table of Contents ; ---------------------
www.eeworm.com/read/210238/7127412

transcript

# Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # do bj_Tw.fdo # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 # --
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hb_cmds

-proj e:\mimasuo -t bj_Tw.tbw -source bjq.vhdl -entity bjq -ipcport 1055
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log coregen.log

# Xilinx CORE Generator 6.2i # User = zsx Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\mimasuo\coregen.log # busformat=BusFormatAngleBracketNotR
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ref hdllib.ref

EN x_lut4 NULL L:/H.39/rtf/vhdl/src/simprims/simprim_VITAL.vhd arch.3410484,3413326.-1 1110312103 AR x_tri x_tri_v L:/H.39/rtf/vhdl/src/simprims/simprim_VITAL.vhd arch.11250176,11252357.-1 1110312278
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prj mode_clk.prj

vhdl work "digital_clk.vhd" vhdl work "page_dclk.vhd" vhdl work "mode_clk.vhd"
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vhdsim_par crc.vhdsim_par

crc.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (VHDL)
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vhdsim_synth crc.vhdsim_synth

crc.vhdsim_synth -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (VHDL)
www.eeworm.com/read/461789/7219858

udo jj.udo

-- ProjNav VHDL simulation template: jj.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands