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downclk.rpt
Project Informationd:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\downclk.rpt
MAX+plus II Compiler Report File
Version 10.12 09/21/2001
Compiled: 12/08/2003 13:16:03
Copyright (C) 1988-2001
left_right_leds.prj
vhdl work "left_right_leds.vhd"
4抽头直接fir滤波器vhdl设计.txt
4抽头直接FIR滤波器VHDL设计
系数为{-1，3.75，3.75，-1}的滤波器的VHDL设计代码经本人综合仿真 如下：
以下内容需要回复才能看到
package eight_bit_int is --user defined types
subtype byte is integer range -128 to 127;
type array_byte is array(0 to
vhdl.fc2
#----------------------------------------------------------
# Synopsys FPGA Compiler II VHDL simulation script vhdl.fc2
# for the book: DSP with FPGAs (2. edition)
# Author-EMAIL: Uwe.Meyer-Baese@
readme.txt
cnt6,count60,counter60.vhd 计数器的图形和VHDL设计
readme.txt
reg4.vhd，reg4_1.vhd,reg8.vhd,add4.gdf,add8.gdf 流水线加法器
mul_8.vhd，mul8.gdf 流水线乘法器
first.vhd,second.vhd 寄存器VHDL优化编码
makedist
rm -f ./doc/* ./src/myhdl/* ./src/vhdl/* turbo.tar.gz
cp ../src/myhdl/*.py ./src/myhdl/
cp ../src/vhdl/*.vhd ./src/vhdl/
#cp ../src/vhdl/compile ./src/vhdl/
#cp ../src/vhdl/*.py ./src/vhdl/
#cp ../src
mc8051_top.cmd_log
ngdbuild -ise "E:/vtest/xilinx/vhdl8051/mc8051/mc8051.ise" -intstyle ise -dd _ngo -nt timestamp -uc "mc8051_top.ucf" -p xc3s500e-fg320-4 "mc8051_top.edn" mc8051_top.ngd
map -ise "E:/vtest/xilinx/vhdl
vhdl源程序.txt
-- 整个电路系统的VHDL源程序
--CDKZQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CDKZQ IS
PORT(CLK_IN:IN STD_LOGIC;
CLR:IN STD_LOGIC;
CHOSE_KEY:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
vhdl.fc2
#----------------------------------------------------------
# Synopsys FPGA Compiler II VHDL simulation script vhdl.fc2
# for the book: Digital Signal Processing with FPGAs
# Author-EMAIL: Uwe.Mey