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找到约 10,970 项符合 VHDL 的代码

buffer_comp.xco

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg

tabla_q.xco

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg

huff_rom.xco

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg

dct2d.xco

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg

syn_dec.inc.txt

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_dec.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

syn_rom.inc.txt

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_rom.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

syn_ctr.inc.txt

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_ctr.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

syn_alu.inc.txt

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_alu.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

syn_ram.inc.txt

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_ram.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.