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100vhdl+
--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
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--------------------------------------------------------------------------------
--
-- FULL adder Benchmark -- Simulation Vectors
--
--
-- Authors :
-- Beijing Institute of Technolog
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--------------------------------------------------------------------------------
--
-- 4-Bit Full Adder
--
-- Benchmark author: Han Shu
--
-------------------------------------------------------
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--***************************************************************************
-- pack.vhdl *
-- VHDL BIT_VECTOR Ope
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package op_pkg is
subtype int3bit is integer range 0 to 7;
end op_pkg;
package synchro is
FUnction rising_edge(signal sig:bit) return boolean;
end synchro;
package body synchro is
100vhdl+
library work;
entity test_pid is
end test_pid;
architecture beh of test_pid is
component fu_pid
port
( reset : in bit;
Fsignin : in bit;
HostInterrupt : in bit;
Positi
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library work;
use work.synchro.all;
use work.op_pkg.all;
----------------------------------------------------------------
entity pid is
port (
reset : in bit;
Fsignin :
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-- Page : 346 - 348
--
-- Objective : dangers of the artificial usage of inout ports
--
-- File Name : test_195.vhd
--
-- Author : Joseph Pick
--
entity Component_Test_195 is