代码搜索结果

#add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib work "../vhdl/addsub_cy_.vhd" add_file -vhdl -lib work "../vhdl/addsub_cy_rtl.vhd" add_file -vhdl -lib work ".

vhdl work "baud.vhd" vhdl work "reciever.vhd" vhdl work "transfer.vhd" vhdl work "uart.vhd"

vhdl work "baud.vhd" vhdl work "reciever.vhd" vhdl work "transfer.vhd" vhdl work "uart.vhd"

work qdq.vhdl

vhdl work qdq.vhdl

## NOTE: Do not edit this file. ## Autogenerated by ProjNav (creatfdo.tcl) on Wed Jun 20 18:35:51 中国标准时间 2007 ## vlib work vcom -93 -explicit qdq.vhdl vcom -93 -explicit ymq.vhdl vcom -93 -ex

EN bjq NULL D:/xilinx仿真/TOP/bjq.vhdl sub00/vhpl00 AR dsq behavioral D:/xilinx仿真/TOP/dsq.vhdl sub00/vhpl03 EN ymq NULL D:/xilinx仿真/TOP/ymq.vhdl sub00/vhpl06 AR bjq behavioral D:/xilinx仿真/TOP/bjq.vhd

V1 40 FL D:/xilinx仿真/TOP/bjq.vhdl 2007/06/11.10:55:26 EN work/BJQ FL D:/xilinx仿真/TOP/bjq.vhdl PB ieee/STD_LOGIC_1164 \ PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED AR work/

# Auto generated by Project Navigator for Modelsim vlib work vcom -93 -explicit qdq.vhdl vcom -93 -explicit ymq.vhdl vcom -93 -explicit bjq.vhdl vcom -93 -explicit dsq.vhdl vcom -93 -expli

vhdl work qdq.vhdl vhdl work ymq.vhdl vhdl work bjq.vhdl vhdl work dsq.vhdl vhdl work fpq.vhdl vhdl work top.vhf