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VHDL 的代码
netlist.lst
D:\work\vhdl\PBLCD\PBLCD.ngc 1174189202
OK
任意整数分频的vhdl代码.vhd
--任意整数分频的VHDL代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clkdiv IS
generic(n:integer:=3);
PORT(
CLK: IN STD_LOGI
run_options.txt
#-- Synplicity, Inc.
#-- Version 9.0
#-- Project file C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\run_options.txt
#-- Written on Fri Mar 14 11:39:52 2008
#add_file options
add_file -vhdl -li
q_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_img.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_comp.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
tabla_q.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
huff_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
dct2d.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
mc8051_compile.do
#!/bin/csh
vcom ../vhdl/mc8051_p.vhd
vcom ../vhdl/control_mem_.vhd
vcom ../vhdl/control_mem_rtl.vhd
vcom ../vhdl/control_mem_rtl_cfg.vhd
vcom ../vhdl/control_fsm_.vhd
vcom ../vhd