代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
www.eeworm.com/read/399143/7886397
ref hdpdeps.ref
V3 16
EN work/MUPSOURCE 0 FL C:/VHDL/MUP/MUPSOURCE.vhd PB ieee/std_logic_1164 1200023565 \
PB ieee/std_logic_arith 1200023566 PB ieee/STD_LOGIC_UNSIGNED 1200023567
AR work/MUPSOURCE/Behaviora
www.eeworm.com/read/398867/7913558
txt 理性分析.txt
这个问题交给市场回答，供求关系决定一切（理性分析）：
现在做视频的很火，说明市场大，更说明门槛低（标准公开），竞争激烈．像中科大样(很完善的体系，有软有硬)和中科软件所下的一家视频公司（用DSP，仅是硬件，算法也使用公开的和他们自己改进的）．
做医疗和遥感图象的也不少，但不如视频的火，关键是算法核，牛人提出的算法交给****徒孙去开发市场与应用（像伟子的那个导师）．
做生物特征( ...
www.eeworm.com/read/297709/8002168
mpf i2c_to_gpio_sim.mpf
[Library]
; Altera specific primitive library mappings
vital2000 = $MODEL_TECH/../vital2000
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
std = $MODEL_TECH/../std
std_develope
www.eeworm.com/read/397462/8046479
qmsg digital6counter.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/397462/8048144
qmsg digital6counter.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/246301/12738770
qmsg key0.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni
www.eeworm.com/read/332117/12777616
xco q_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg
www.eeworm.com/read/332117/12777629
xco buffer_img.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg
www.eeworm.com/read/332117/12777659
xco buffer_comp.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg
www.eeworm.com/read/332117/12777700
xco tabla_q.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coreg