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VHDL 的代码
vhdl.npl
JDF E
// Created by ISE ver 1.0
PROJECT vhdl
DESIGN vhdl Normal
DEVKIT XCR3256XL CS280
DEVFAM xpla3
FLOW XST VHDL
STIMULUS multi_dvm_tb.vhd Normal
STIMULUS top_level_tb.vhd Normal
MODULE top_
top_level_tb.udo
## Project Navigator VHDL simulation template: top_level_tb.udo
## You may edit this file to control your simulation.
readme.txt
---------------------------------------------------------
- Readme for VHDL and Verilog source code -
---------------------------------------------------------
The design was target
fft64_xfft_v4_1_xst_1_vhdl.prj
vhdl baseblox_utils_v9_1 "E:\FPGA\FPGA_Prog\study_FFTcore\tmp\_cg\_bbx\baseblox_utils_v9_1\prims_constants_v9_1.vhd"
vhdl baseblox_utils_v9_1 "E:\FPGA\FPGA_Prog\study_FFTcore\tmp\_cg\_bbx\baseblox_ut
core_fft64_xfft_v4_1_xst_1_vhdl.prj
vhdl baseblox_utils_v9_1 "E:\FPGA\FPGA_Prog\study_FFTcore\tmp\_cg\_bbx\baseblox_utils_v9_1\prims_constants_v9_1.vhd"
vhdl baseblox_utils_v9_1 "E:\FPGA\FPGA_Prog\study_FFTcore\tmp\_cg\_bbx\baseblox_ut
说明.txt
此为实验四 分频电路与12归1电路设计例程：
1、twelveto1为12归1 AHDL 电路参考程序。
2、twelveto1v为12归1 VHDL电路参考程序。
其中时钟输入inclk\finclk为芯片P183脚（50M），显示输出outputa0--outputa6分别对应芯片p168、p167、p166、p164、p163、p162、p161脚,outputbo--outpu
tone.prj
vhdl work "tune.vhd"
top_vhdl.prj
vhdl work "G:\ISE9.1\menling\MUSIC.vhd"
vhdl work "G:\ISE9.1\menling\tune.vhd"
vhdl work "G:\ISE9.1\menling\SPEAKER.vhd"
vhdl work "G:\ISE9.1\menling\NoteTabs.vhd"
vhdl work "G:\ISE9.1\menling\TOP
notetabs.prj
vhdl work "MUSIC.vhd"
vhdl work "NoteTabs.vhd"
notetabs_vhdl.prj
vhdl work "G:\ISE9.1\menling\MUSIC.vhd"
vhdl work "G:\ISE9.1\menling\NoteTabs.vhd"