代码搜索结果

-proj f:\dianzijishushiyan-dodo\fenpin -t wave.tbw -source fenpin1.vhdl -entity fenpin1 -ipcport 3130

[General Information] 书名=VHDL实用教程 作者= 页数=339 SS号=10205352 出版日期=

-- ProjNav VHDL simulation template: Test.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

ata/rtl/vhdl/ocidec3

JDF E // Created by ISE ver 1.0 PROJECT game2 DESIGN game2 Normal DEVKIT xc2s100-5tq144 DEVFAM spartan2 FLOW XST VHDL MODULE Count64.vhd MODSTYLE count64 Normal MODULE target.vhd MODSTYLE ta

[General Information] 书名=VHDL语言100例详解 作者= 页数=494 SS号=10110347 出版日期=

-- ProjNav VHDL simulation template: hghm.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

vhdl work "C:\rahul\parityassign\parity.vhd"

-file "C:\rahul\parityassign\dff1.dia" -lang vhdl -vend xst

vhdl work "parity.vhd"