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-- ProjNav VHDL simulation template: jj.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

Release 7.1.04i - netgen H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim led.nga led_timesim.vhd Reading d

-- ProjNav VHDL simulation template: ss.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands

Release 7.1.04i - netgen H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim led.nga led_timesim.vhd Reading d

led.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (VHDL)

Release 7.1.04i - netgen H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim a90541.nga a90541_timesim.vhd Rea

vhdl work "90541.vhd"

Release 7.1.04i - netgen H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim a90541.nga a90541_timesim.vhd Rea

vhdl work "led.vhd"

vhdl work "led.vhd"