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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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rpt dds_vhdl.fit.rpt

Fitter report for dds_vhdl Sat Sep 03 15:19:15 2005 Version 4.1 Build 181 06/29/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2.
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rpt dds_vhdl.tan.rpt

Timing Analyzer report for dds_vhdl Sat Sep 03 15:19:23 2005 Version 4.1 Build 181 06/29/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Not
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summary dds_vhdl.tan.summary

-------------------------------------------------------------------------------------- Timing Analyzer Summary --------------------------------------------------------------------------------------
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db_info dds_vhdl.db_info

Quartus_Version = Version 6.0 Build 178 04/27/2006 SJ Full Version Version_Index = 67154432 Creation_Time = Wed May 30 14:02:37 2007
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cdb dds_vhdl.eco.cdb

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qrpt dds_vhdl_cmp.qrpt

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rpt dds_vhdl.asm.rpt

Assembler report for dds_vhdl Sat Sep 03 15:19:20 2005 Version 4.1 Build 181 06/29/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice
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summary dds_vhdl.fit.summary

Flow Status : Successful - Sat Sep 03 15:19:15 2005 Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version Revision Name : dds_vhdl Top-level Entity Name : DDS_VHDL Family : Cyclone Device
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rpt dds_vhdl.flow.rpt

Flow report for dds_vhdl Sat Sep 03 15:19:23 2005 Version 4.1 Build 181 06/29/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. F
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eqn dds_vhdl.map.eqn

--S1_q_a[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[9] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Wid
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