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VHDL 的代码
q_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_img.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_comp.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
tabla_q.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
huff_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
dct2d.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
add_files.tcl
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/Cordic/hdl/shiftn_synthesis.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/Cordic/hdl/addsub_synthesi
hdllib.ref
EN ex3 NULL F:/7-segment/ex3.vhdl sub00/vhpl00
AR ex3 behavioral F:/7-segment/ex3.vhdl sub00/vhpl01
hdpdeps.ref
V1 4
FL F:/7-segment/ex3.vhdl 2009/04/09.13:08:54
EN work/EX3 FL F:/7-segment/ex3.vhdl PB ieee/STD_LOGIC_1164 \
PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/EX3/BEH
ex3.prj
vhdl work ex3.vhdl