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summary dds_vhdl.fit.summary

Flow Status : Successful - Sat Sep 10 08:45:24 2005 Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version Revision Name : dds_vhdl Top-level Entity Name : DDS_VHDL Family : Cyclone Device
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rpt dds_vhdl.flow.rpt

Flow report for dds_vhdl Sat Sep 10 08:45:35 2005 Version 4.1 Build 181 06/29/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. F
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eqn dds_vhdl.map.eqn

--SB1_q_a[9] is SIN_ROM:u3|altsyncram:altsyncram_component|altsyncram_gmu:auto_generated|altsyncram_8kc2:altsyncram1|q_a[9] --RAM Block Operation Mode: True Dual-Port --Port A Depth: 1024, Port A Wi
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vhdl std_logic_signed.vhdl

-------------------------------------------------------------------------- -- -- -- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc
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vhdl std_logic_unsigned.vhdl

-------------------------------------------------------------------------- -- -- -- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc
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vhdl std_logic_arith.vhdl

-------------------------------------------------------------------------- -- -- -- Copyright (c) 1990,1991,1992 by Synopsys, Inc.
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vhdl std_logic_misc.vhdl

-------------------------------------------------------------------------- -- -- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved. -- -- This source file may be used and distribu
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vhdl std_logic_textio.vhdl

---------------------------------------------------------------------------- -- -- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved. -- -- This source file may be used and distri
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vhdl math_complex-body.vhdl

--------------------------------------------------------------- -- -- This source file may be used and distributed without restriction. -- No declarations or definitions shall be included in this pac
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vhdl std_logic_1164.vhdl

-- -------------------------------------------------------------------- -- -- Title : std_logic_1164 multi-value logic system -- Library : This package shall be compiled into a library --
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