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dds_vhdl.tan.rpt
Classic Timing Analyzer report for DDS_VHDL
Sun Aug 10 19:36:24 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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dds_vhdl.map.rpt
Analysis & Synthesis report for DDS_VHDL
Sun Aug 10 19:36:10 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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my_ram_vhdl.vhd
-- Quartus II VHDL Template
-- Single port RAM with single read/write address
library ieee;
use ieee.std_logic_1164.all;
entity my_ram_vhdl is
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDT
vhdl2vl.ini
C:\Program Files\UltraEdit\Uedit32.exe
0
0
vhdl2vl.txt
VHDL to Verilog RTL transformer
In 1.0 version ,
some functions restricted, as follows:
1: not all support "Generate" statement,totally not support "if .. Generate "
2: Comment in vhdl may have