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vhdl1.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count is
port(clk,clr,en:in std_logic;
q: out std_logic_vector (3
dds_vhdl.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC; --系统时钟
FWOR
dds_vhdl.fit.smsg
Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Extra Info: