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vhdl.txt
5-1加法器(减法器电路设计
5-1-1全加器电路
--fadd.vhd fadd.vhd one bit full adder
library ieee ;
use ieee.std_logic_1164.all;
entity fadd is
port(
a: in std_logic;--被加数
b: in std_logic;---加数
ci : in std
textio.vhdl
-- Std.Textio package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold
--
-- GHDL is