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VHDL 的代码
wave_vhdl.do
add wave -noupdate -format Logic /testbnch/PCLK
add wave -noupdate -format Logic /testbnch/PRESETN
add wave -noupdate -format Literal /testbnch/UARTstatus1_data_out
add wave -noupdate -format Logic
lcd1602.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity char_ram is
port( address : in std_logic_vector(5 downto 0) ;
data : out std_logic_vector(7 downto 0)
);
63_vhdl.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_gcd_disp is
end t
56_vhdl.vhd
-- Author : yzf
-- Created On: Tue Dec 12 08:26:19 1995
-- Testbench for prefetch.prefetch
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_prefetch is
end t
lcd1602.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity char_ram is
port( address : in std_logic_vector(5 downto 0) ;
data : out std_logic_vector(7 downto 0)
);
sram.vhdl.hmm
------------------------------------------------------------------------
-- sram.vhd -- Synchronous SRAM interface
------------------------------------------------------------------------
-- Auth
vga_vhdl.prj
work "vga.vhd"
63_vhdl.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_gcd_disp is
end t
56_vhdl.vhd
-- Author : yzf
-- Created On: Tue Dec 12 08:26:19 1995
-- Testbench for prefetch.prefetch
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_prefetch is
end t
lcd1602.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity char_ram is
port( address : in std_logic_vector(5 downto 0) ;
data : out std_logic_vector(7 downto 0)
);