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sram_vhdl.prj
work sram2.vhd
vhdl1.vhd
-- Quartus VHDL Template
-- State Machine with Asynchronous Reset (1 block)
-- State Machine outputs will be registered
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY vhdl1 IS
PORT
(
yle270.vhdl
--*****************************************************************************
-- 版权所有(c) 2006, 深圳市优龙科技有限公司
-- 保留所有权利
--
-- 文件: YLE270.vhdl
-- 描述: YL-E270 DEV v1.0板的CPLD器件的源代码
-- 器件
top_1.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
top_2.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
top_1.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
mti_vhdl.do
#----------------------------------------------------------
# Model Technology VHDL compiler script for the book
# Digital Signal Processing with FPGAs (2.edition)
# Author-EMAIL: Uwe.Meyer-B