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VHDL 的代码
vhdl1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds is
port(
clk:in std_logic;
en:in std_logic;
address:out integer range 0 to 4095
);
architecture a
wand_vhdl.vhd
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package res_pack is
function res_func(data : in bit_vector)return bit;
end;
package body res_pack is
function re
rs232.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RS232 is
port(
nReset : in std_logic;
gCLK