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VHDL 的代码
vhdl.txt
/L12"VHDL" Line Comment = -- Nocase String Chars = " File Extensions = VHD VHO VHDL
/Delimiters = ; ( )'=:+/-*|&,
/Indent Strings = "entity" "architecture" "component" "begin" "(" "if" "case" "els
vhdl.txt
--fadd.vhd fadd.vhd one bit full adder
library ieee ;
use ieee.std_logic_1164.all;
entity fadd is
port(
a: in std_logic;
b: in std_logic;
ci : in std_logic;
co: out std_logic;
vhdl.txt
5-1
vhdl.txt
5-1加法器(减法器电路设计
5-1-1全加器电路
--fadd.vhd fadd.vhd one bit full adder
library ieee ;
use ieee.std_logic_1164.all;
entity fadd is
port(
a: in std_logic;--被加数
b: in std_logic;---加数
ci : in std