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VHDL 的代码
memoire_alphabet.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.NUMERIC_STD.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components
vhdl93.txt
/L20"VHDL" DisableMLS Line Comment = -- Nocase String Chars = " File Extensions = VHD VHO
/Delimiters = ; ( )'=:+-/*|&
/C1"VHDL reserved words"
abs access after alias all and architecture array a
top_vhdl.prj
vhdl work "F:\project\CPU16\memory.vhd"
vhdl work "F:\project\CPU16\mem1.vhd"
vhdl work "F:\project\CPU16\kernel.vhd"
vhdl work "F:\project\CPU16\four.vhd"
vhdl work "F:\project\CPU16\cache.vhd"
vhdl-adder.txt
VHDL加法器
-- N-bit adder
-- The width of the adder is determined by generic N
library IEEE;
use IEEE.std_logic_1164.all;
entity adderN is
generic(N : integer := 16);
port (a :