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100vhdl+
--Page :307,308
--Objective :'TRANSACTION and reso;ved signals
--Filename :test_74.vhd
--Author :Joseph Pick
--Update :cdy 1998 4
entity Test_74s is
end
100vhdl+
library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity tb_buffer is
end tb_buffer;
architecture test of tb_buffer is
component key_buffer
port(key:in t_digital;
c
100vhdl+
-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
100vhdl+
-- _ _
-- L
---------------------------OO-------OO---------------------------------
--
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package mycntpkg is
component count port(clk,rst : in std_logic;
cnt : inout std_logic_vector(2 downto 0));
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end testcnt;
use work.mycntpkg.all;
architecture mytest of testcnt is
signal clk,rst:std_logic;
signal cnt:std_logic_vector(2 d
100vhdl+
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------
entity B_CONST1 is
-----------------------------------------------------------
generic
(
NU