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100vhdl+

library IEEE; use IEEE.std_logic_1164.all; library dsp_lib; use dsp_lib.delay_macro.all; use dsp_lib.logic_pack.all; use dsp_lib.const_pack.all; ------------------------------------------ ent

100vhdl+

-- Page : 353 - 354 -- -- Objective : array signal multiplexing : error -- -- File Name : test_35b.vhd -- -- Author : Joseph Pick -- entity Test_35b is end Test_35b; archi

100vhdl+

-------------------------------------------------------------------------------- -- -- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks) -- -- Source: AMD data book

100vhdl+

-------------------------------------------------------------------------------- -- -- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks) -- -- Source: AMD data book

100vhdl+

-- The eneity declaration of INVERTER ------------------------ entity B_INV is ------------------------ port( I1 : in bit; O1 : out bit ); end B_INV; -- The archit

100vhdl+

-- (C) Copyright 1996 Doulos All Rights Reserved -- Solution for Counter library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Std_logic_arith.all; entity DIVIDER is port (CLK_IN : in Std

100vhdl+

--written by Diao Lan Song --1998/9/25 library IEEE; use IEEE.std_logic_1164.all; use IEEE.Std_logic_arith.all; entity Stimulus is end Stimulus; architecture test_bench of Stimulus is