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VHDL 的代码
lcd_vhdl2.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD is
port( clk:in std_logic;
rs: out std_logic;
rw: out std_logic;
ffd_vhdl_vhdl.txt
--
--
------------------------------------------------------------------------------------
-- DESCRIPTION : Flip-flop D type
-- Width: 8
-- Clock active: high