代码搜索：U盘设计

找到约 10,000 项符合「U盘设计」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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prjpcb u盘电路设计.prjpcb

[Design] Version=1.0 HierarchyMode=0 OutputPath= OpenOutputs=1 ArchiveProject=0 TimestampOutput=0 SeparateFolders=0 AllowPortNetNames=0 AllowSheetEntryNetNames=1 [Document1] DocumentPath=Pc
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www.eeworm.com/read/217265/14972239

schlib u盘电路设计.schlib

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www.eeworm.com/read/217265/14972241

prjpcbstructure u盘电路设计.prjpcbstructure

Record=TopLevelDocument|FileName=U盘电路设计.SCHDOC
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www.eeworm.com/read/217265/14972243

txt u盘电路设计.txt

Field=Designator,String,Designator,100|Field=LibRef,String,LibRef,100|Field=Description,String,Description,100|Field=Footprint,String,Footprint,100|Field=Comment,String,Comment,100 C1|Cap Semi|Capaci
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www.eeworm.com/read/217265/14972244

xls u盘电路设计.xls

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www.eeworm.com/read/217265/14972248

net u盘电路设计.net

[ C1 CC1310-0504 Cap Semi ] [ C2 CC1310-0504 Cap Semi ] [ C3 CC1310-0504 Cap Semi ] [ C4 CC1310-0504 Cap Semi ] [ C5 CC1310-0504 Cap Semi ] [ C6
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www.eeworm.com/read/19014/807140

schdoc u盘电路设计.schdoc

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www.eeworm.com/read/19014/807144

pcbdoc u盘电路设计.pcbdoc

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www.eeworm.com/read/19014/807145

drc u盘电路设计.drc

Protel Design System Design Rule Check PCB File : \Protel DXP 2004\Design\chapter13\U盘电路设计.PCBDOC Date : 2005-5-22 Time : 16:21:22 Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3
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www.eeworm.com/read/19014/807147

prjpcb u盘电路设计.prjpcb

[Design] Version=1.0 HierarchyMode=0 OutputPath= OpenOutputs=1 ArchiveProject=0 TimestampOutput=0 SeparateFolders=0 AllowPortNetNames=0 AllowSheetEntryNetNames=1 [Document1] DocumentPath=Pc
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