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test.v
// Testbench for Micron SDR SDRAM Verilog models
`timescale 1ns / 1ps
module test;
reg [31 : 0] dq; // SDRAM I/O
reg [10 : 0] addr;
test.tag
Var 1Var 2Var 3Var 4Var 5Var 6
test.dat
2.5972184e+000 6.5728282e-001 4.9495354e-001 7.5675678e-001 1.4984104e-002 9.5654951e-001
3.0712034e+000 9.5234475e-001 6.8411411e-001 8.1114819e-001 8.3783354e-001 7.2769071e-001
3.
test.c
//---------------------------------------------------------------------
// File: test.c
//
// Written By: Lawrence Glaister VE7IT
//
// Purpose: This set of routines deals with various test
//