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Test 的代码
test.v
`timescale 1ns/1ps
module Test;
reg clk;
reg rst_n;
reg [31:0] A_in;
reg [31:0] B_in;
wire [31:0] final_out;
always #2.5 cl
test.txt
0,0
0,1
0,2
0,3
1,0
1,1
1,2
1,3
2,0
2,1
2,2
2,3
3,0
3,1
3,2
3,3
test.cmd
-w
-stack 500
-sysstack 500
-l rts55x.lib
MEMORY
{
DARAM: o=0x100, l=0x7f00
VECT : o=0x8000, l=0x100
DARAM2: o=0x8100, l=0x7f00
SARAM: o=0x10000, l=0x30000
SDRAM: o=
test.txt
this is a test file