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Warning (10268): Verilog HDL information at lcd.v(76): always construct contains both blocking and non-blocking assignments Warning (10268): Verilog HDL information at lcd.v(89): always construct con

[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1 [ProjectWorkspace.Frames.

Extra Info: Performing register packing on registers with non-logic cell location assignments Extra Info: Completed register packing on registers with non-logic cell location assignments Extra Info:

# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2010 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # an

Wed Jan 12 20:45:55 2011

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