代码搜索：Synchronous
找到约 1,924 项符合「Synchronous」的源代码
代码结果 1,924
www.eeworm.com/read/233751/14141216
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/206041/15302070
txt fifo.v.txt
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/206041/15302082
v fifo_2.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/8785/153261
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/13605/279592
txt fifo.v.txt
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/13605/279604
v fifo_2.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/17812/761337
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/17870/763405
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/17893/765823
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/18104/775040
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad