代码搜索：Synchronous
找到约 1,924 项符合「Synchronous」的源代码
代码结果 1,924
www.eeworm.com/read/430518/1923835
h memreg.h
/* $Id: memreg.h,v 1.8 1996/08/29 09:48:23 davem Exp $ */
#ifndef _SPARC_MEMREG_H
#define _SPARC_MEMREG_H
/* memreg.h: Definitions of the values found in the synchronous
* and asynchronou
www.eeworm.com/read/411765/2183310
vhd wr_gray_cntr.vhd
-- fifo_wr_addr gray counter with synchronous reset
-- Gray counter is used for FIFO address counter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-- pragma transla
www.eeworm.com/read/411765/2183708
v rd_gray_cntr.v
//-- fifo_rd_addr gray counter with synchronous reset
`timescale 1ns/100ps
module rd_gray_cntr (
clk,
reset,
cnt_en,
rgc_gcnt
);
input clk;
input re
www.eeworm.com/read/357083/3029366
h memreg.h
/* $Id: memreg.h,v 1.8 1996/08/29 09:48:23 davem Exp $ */
#ifndef _SPARC_MEMREG_H
#define _SPARC_MEMREG_H
/* memreg.h: Definitions of the values found in the synchronous
* and asynchronou
www.eeworm.com/read/389033/8552240
v fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/387421/8685004
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/429621/8798444
m m5.m
% MATLAB script file m5.m file for Project 5 on a 2X3
% synchronous machine model having three rotor circuits
% with coupling in Chapter 7
% m5.m does the following:
% loads machine param
www.eeworm.com/read/282829/9056977
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/380806/9127666
v fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/351504/10645192
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad