代码搜索：Synchronous
找到约 1,924 项符合「Synchronous」的源代码
代码结果 1,924
www.eeworm.com/read/464109/7169612
m i3essr.m
% MATLAB script file to load synchronous machine
% parameters given in Table 1 of First Benchmark Model
% for Computer Simulation of Subsynchronous Resonance
% IEEE Trans on PAS, Vol. 1, PA
www.eeworm.com/read/457723/7318716
vhd serial.vhd
--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--****************************************************
www.eeworm.com/read/289562/7805621
10 fig3.10
#include "apue.h"
#include
int
main(int argc, char *argv[])
{
int val;
if (argc != 2)
err_quit("usage: a.out ");
if ((val = fcntl(atoi(argv[1]), F_GETFL, 0)) < 0)
err
www.eeworm.com/read/289562/7805662
c fileflags.c
#include "apue.h"
#include
int
main(int argc, char *argv[])
{
int val;
if (argc != 2)
err_quit("usage: a.out ");
if ((val = fcntl(atoi(argv[1]), F_GETFL, 0)) < 0)
err
www.eeworm.com/read/399935/7821063
v counters.v
// MAX+plus II Verilog Example
// Efficient Counter Inference
// Copyright (c) 1997 Altera Corporation
module counters (d, clk, clear, ld, enable, up_down,
qa, qb, qc, qd, qe, qf, q
www.eeworm.com/read/198616/7922852
10 fig3.10
#include "apue.h"
#include
int
main(int argc, char *argv[])
{
int val;
if (argc != 2)
err_quit("usage: a.out ");
if ((val = fcntl(atoi(argv[1]), F_GETFL, 0)) < 0)
err
www.eeworm.com/read/198616/7922962
c fileflags.c
#include "apue.h"
#include
int
main(int argc, char *argv[])
{
int val;
if (argc != 2)
err_quit("usage: a.out ");
if ((val = fcntl(atoi(argv[1]), F_GETFL, 0)) < 0)
err
www.eeworm.com/read/332098/12779658
10 fig3.10
#include "apue.h"
#include
int
main(int argc, char *argv[])
{
int val;
if (argc != 2)
err_quit("usage: a.out ");
if ((val = fcntl(atoi(argv[1]), F_GETFL, 0)) < 0)
err
www.eeworm.com/read/332098/12779777
c fileflags.c
#include "apue.h"
#include
int
main(int argc, char *argv[])
{
int val;
if (argc != 2)
err_quit("usage: a.out ");
if ((val = fcntl(atoi(argv[1]), F_GETFL, 0)) < 0)
err
www.eeworm.com/read/243541/12934983
v counters_altera.v
// MAX+plus II Verilog Example
// Efficient Counter Inference
// Copyright (c) 1997 Altera Corporation
// download from: www.pld.com.cn & www.fpga.com.cn
module counters (d, clk, clear, ld, ena