代码搜索：Stuart
找到约 1,422 项符合「Stuart」的源代码
代码结果 1,422
www.eeworm.com/read/405708/11458962
sv 02.03.03_snippet-1.sv
/**********************************************************************
* Code snippet showing declaration order dependency with $unit space
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003,
www.eeworm.com/read/405708/11458964
sv 02.08.00_snippet-2.sv
/**********************************************************************
* Automatic declarations within a static function
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003, Sutherland HDL, Inc
www.eeworm.com/read/405708/11458966
sv 02.02.00_snippet-2.sv
/**********************************************************************
* Code snippet showing `define `" macro enhancements
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003, Sutherland HDL,
www.eeworm.com/read/405708/11458968
sv 02.03.00_example_2-1.sv
/**********************************************************************
* external ($unit) defintions and declarations
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003, Sutherland HDL, Inc. *
www.eeworm.com/read/405708/11458973
sv 05.02.01_example_5-1.sv
/**********************************************************************
* FSM using always @() -- only triggers on changes in sensitivity list
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003
www.eeworm.com/read/405708/11458976
sv 05.03.03_snippet-3.sv
/**********************************************************************
* Using function name as temporary storage with return keyword
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003, Suther
www.eeworm.com/read/405708/11458979
sv 05.02.01_snippet-2.sv
/**********************************************************************
* always_comb procedure with incomplete if statement (latched logic)
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003,
www.eeworm.com/read/405708/11458989
sv 05.03.09_snippet-4.sv
/**********************************************************************
* Task args with implicit input direction
* (SystemVerilog style)
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003, Su
www.eeworm.com/read/405708/11458993
sv 05.03.09_snippet-3.sv
/**********************************************************************
* Task args with explicitly declared input direction
* (Verilog style)
*
* Author: Stuart Sutherland
*
* (c) Copyright 200
www.eeworm.com/read/405708/11459005
sv 04.03.06_snippet-2.sv
/**********************************************************************
* Assigning unpacked arrays to unpacked arrays (legal)
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003, Sutherland HDL