代码搜索：Step
找到约 10,000 项符合「Step」的源代码
代码结果 10,000
www.eeworm.com/read/157516/11696871
m mysd.m
% Jun.9,1999, a subroutine of SSD.m
% use Accelerated Subgradient Update method
function [gam]=mySD(c)
n=size(c);
S=ndims(c);
if S==2
gam=[1:n(1)]';
[J,omiga,assign]=auction(-c);
www.eeworm.com/read/156908/11752854
c config.c
/*
* MIRACL utility program to automatically generate a mirdef.h file
*
* config.c
*
* Compile WITHOUT any optimization
*
* Run this with your computer/compiler configuration. I
www.eeworm.com/read/259565/11781836
m s_log2reflectivity.m
function reflect=s_log2reflectivity(wlog,step,varargin)
% Create reflection coefficient series in time from well log in
% depth or time. An impedance curve to use can be specified via the
% "redefine
www.eeworm.com/read/259565/11781910
m s_convolve.m
function seismic=s_convolve(seisin1,seisin2,varargin)
% Function convolves two seismic data sets
% If one of the data sets has only one trace then it is convolved with all
% traces of the other data
www.eeworm.com/read/259565/11781998
m s_new_time.m
function seismic=s_new_time(seismic,old_new,varargin)
% Function creates new "time" scale (e.g. for time-to-depth conversion: in
% this case the first column would be times and the second columns the
www.eeworm.com/read/156426/11804817
m bpsan.m
clear
x1=linspace(0.0001,2*pi,11);
y1=linspace(0.0001,2*pi,11); %初始化输入值X1 Y1
[x1,y1]=meshgrid(x1,y1);
d=(((sin(x1).*sin(y1))./(x1.*y1))+1)/2; %初始化输出d
w1=[1.5844 1.6441;
www.eeworm.com/read/259112/11820230
m dwindow.m
function Dh=dwindow(h);
%DWINDOW Derive a window.
% DH=DWINDOW(H) derives a window H.
%
% Example :
% plot(dwindow(tftb_window(210,'hanning')))
%
% See also WINDOW.
% F. Auger, August 1994, July 19
www.eeworm.com/read/155919/11838419
m cp0802_pdp.m
%
% FUNCTION 8.10 : "cp0802_PDP"
%
% Evaluates the Power Delay Profile 'PDP'
% of a channel impulse response 'h' sampled
% at frequency 'fc'
%
% Programmed by Guerino Giancola
%
function [P
www.eeworm.com/read/345051/11843394
v sel.v
module SEL(
iCLK,
SW,
Step
);
input iCLK;
input [2:0] SW;
wire [2:0] SW;
output [7:0] Step ;
reg [7:0] Step ;
always @(posedge iCLK)
begin
case(SW)
3'b000:
Step