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State Machine 的代码
mcu_sram_test.smp_dump.txt
State Machine - |mcu_sram_test|osc:inst2|osc_control:inst|state
Name state.WAIT2 state.WAIT1 state.ALLIN state.IDLE
state.IDLE 0 0 0 0
state.WAIT1 0 1 0 1
state.ALLIN 0 0 1 1
state.WAIT2 1
dingceng.smp_dump.txt
State Machine - |jiaotongdeng|current_state
Name current_state~16 current_state~15 current_state~14
current_state.state0 0 0 0
current_state.state6 1 1 0
current_state.state5 1 0 1
current_
jiaotongdeng.smp_dump.txt
State Machine - |dingceng|jiaotongdeng:inst|current_state
Name current_state~16 current_state~15 current_state~14
current_state.state0 0 0 0
current_state.state6 1 1 0
current_state.state5 1
xkcon.smp_dump.txt
State Machine - |xkcon|c_st
Name c_st~13 c_st~12 c_st~11
c_st.st0 0 0 0
c_st.st1 0 0 1
c_st.st2 0 1 0
c_st.st3 0 1 1
c_st.st4 1 0 0
lcd1602.smp_dump.txt
State Machine - |LCD1602|Current_State
Name Current_State~45 Current_State~44 Current_State~43 Current_State~42 Current_State~41
Current_State.set_dlnf 0 0 0 0 0
Current_State.set_cursor 0 0 0
adc.smp_dump.txt
State Machine - |adc|state1
Name state1~8 state1~7
state1.st0 0 0
state1.st2 1 0
state1.st1 0 1
state1.st3 1 1
test_rec.smp_dump.txt
State Machine - |test_rec|state
Name state.11 state.01 state.10 state.00
state.00 0 0 0 0
state.10 0 0 1 1
state.01 0 1 0 1
state.11 1 0 0 1
sent.smp_dump.txt
State Machine - |sent|txd:inst2|n
Name n.1001 n.0001 n.0010 n.0011 n.0100 n.0101 n.0110 n.0111 n.1000 n.0000
n.0000 0 0 0 0 0 0 0 0 0 0
n.1000 0 0 0 0 0 0 0 0 1 1
n.0111 0 0 0 0 0 0 0 1 0 1
txd.smp_dump.txt
State Machine - |txd|n
Name n.1001 n.0001 n.0010 n.0011 n.0100 n.0101 n.0110 n.0111 n.1000 n.0000
n.0000 0 0 0 0 0 0 0 0 0 0
n.1000 0 0 0 0 0 0 0 0 1 1
n.0111 0 0 0 0 0 0 0 1 0 1
n.0110 0 0
vhdl1.vhd
-- Quartus VHDL Template
-- State Machine with Asynchronous Reset (1 block)
-- State Machine outputs will be registered
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY vhdl1 IS
PORT
(