代码搜索结果

source "C:/eda/synplicity/fpga_81/lib/altera/quartus_cons.tcl" syn_create_and_open_prj state2 source $::quartus(binpath)/prj_asd_import.tcl syn_create_and_open_csf state2 syn_handle_cons state2

#Begin clock constraint define_clock -name {b:state2_default|clk} -period 2.746 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 1.373 -route 0.000 #End clock constraint

/** * Physical Layer Management Entity-Service Access Point * PLME-SAP - PLME-SET_TRX_STATE * * @author IPP HURRAY http://www.hurray.isep.ipp.pt/art-wise * @author Andre Cunha * */ in

function A = add_hhmm_end_state(transprob, termprob) % ADD_HMM_END_STATE Combine trans and term probs into transmat for automaton with an end state % function A = add_hhmm_end_state(transprob, termp

function [transprob, termprob] = remove_hhmm_end_state(A) % REMOVE_END_STATE Infer transition and termination probabilities from automaton with an end state % [transprob, termprob] = remove_end_stat

function [transprob, termprob] = remove_hhmm_end_state(A) % REMOVE_END_STATE Infer transition and termination probabilities from automaton with an end state % [transprob, termprob] = remove_end_stat

AVR323 Interfacing GSM modems: STATE_function

AVR323 Interfacing GSM modems: STATE_function