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State Machine 的代码
lexer_shared_input_state.sa
(*
ANTLR Translator Generator
Project led by Terence Parr at http://www.jGuru.com
Software rights: http://www.antlr.org/RIGHTS.html
$Id: //depot/code/org.antlr/release/antlr-2.7.0/lib/sath
ex6_3_state.m
function stst = Ex6_3_state(t,y)
% set up the state equations as a col vector
% the previous state is known in y
% the first order derivatives is returned
% in the variable name used to the le
ex5_3_state.m
function stst = Ex5_3_state(t,y)
% set up the state equations as a col vector
% the previous state is input as y
% the first order derivatives is returned
% in the variable name used to the le
state variable represent to h(z).m
% ------------------------------------------------------------------------------
% exa050905_tf2ss.m , for example 5.9.5
% to test tf2ss.m and ss2tf.m, to realize the conversion between H(z) and it
assert_quiescent_state_logic.v
// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.
parameter assert_name = "ASSERT_QUIESCENT_STATE";
`include "std_ovl_task.h"
assert_quiescent_state_logic.sv
// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.
parameter assert_name = "ASSERT_QUIESCENT_STATE";
`include "std_ovl_task.h"
ddr_lvds_3state.v
//
// Module: DDR_LVDS_3STATE
//
// Description: Verilog Instantiation Template
// DDR 3-State Flip-Flops with LVDS 3-State output buffer
//
//
// Device: VIRTEX-II Family
//
//---
state variable represent to h(z).m
% ------------------------------------------------------------------------------
% exa050905_tf2ss.m , for example 5.9.5
% to test tf2ss.m and ss2tf.m, to realize the conversion between H(z) and it