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找到约 10,000 项符合 State Machine 的代码

targets.mk

# $Id: targets.mk,v 1.2 1996/01/16 14:21:00 chris Exp $ # # Targets.mk for Network Kernel library (libnet.a) # CPU =R4000 include $(LSIPKG)/$(CPU)mips2.mk # Machine type(s) MACHINE =$(CPUFLGS) # T

targets.mk

# $Id: targets.mk,v 1.2 1996/01/16 14:20:56 chris Exp $ # # Targets.mk for Network Kernel library (libnet.a) # CPU =R4000 include $(LSIPKG)/$(CPU).mk # Machine type(s) MACHINE =$(CPUFLGS) # Target

2161.cpp

/* This Code is Submitted by wywcgs for Problem 2161 on 2006-03-08 at 17:00:12 */ #include #include using namespace std; const int MAX = 320; class Machine { public:

2161.cpp

/* This Code is Submitted by wywcgs for Problem 2161 on 2006-03-08 at 17:00:12 */ #include #include using namespace std; const int MAX = 320; class Machine { public:

malformedpacketexception.java

// PART OF THE MACHINE SIMULATION. DO NOT CHANGE. package nachos.machine; /** * Thrown when a malformed packet is processed. */ public class MalformedPacketException extends Exception { /**

http:^^www.cs.cornell.edu^info^courses^current^cs211^course-material.html

MIME-Version: 1.0 Server: CERN/3.0 Date: Sunday, 24-Nov-96 22:34:25 GMT Content-Type: text/html Content-Length: 827 Last-Modified: Monday, 07-Oct-96 14:40:54 GMT Course Material

103.txt

Rule: -- Sid: 103 -- Summary: Subseven22 is a Trojan Horse. -- Impact: Possible theft of data and control of the targeted machine leading to a compromise of all resources the machine is connected

107.txt

Rule: -- Sid: 107 -- Summary: Subseven22 is a Trojan Horse. -- Impact: Possible theft of data and control of the targeted machine leading to a compromise of all resources the machine is connected

get_names.c

/* * Copyright (c) 1983 Regents of the University of California. * All rights reserved. The Berkeley software License Agreement * specifies the terms and conditions for redistribution. */ #inclu

de2_lcm_test.smp_dump.txt

State Machine - |DE2_LCM_Test|I2S_LCM_Config:u4|mSetup_ST Name mSetup_ST.0000 mSetup_ST.0010 mSetup_ST.0001 mSetup_ST.0000 0 0 0 mSetup_ST.0001 1 0 1 mSetup_ST.0010 1 1 0