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# # Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R. # # Period Constraints FREQUENCY PORT "clk" 364.2 MHz; # Output Constraints # Input Constraints BLOCK ASYNCPATHS;

(edif state2_default (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2005 12 16 16 56 10) (author "Synplicity, Inc.")

Selecting top level module state2_default @N:"C:\prj\FSM_abc\state_default\state2_default.v":2:7:2:20|Synthesizing module state2_default @N: CL201 :"C:\prj\FSM_abc\state_default\state2_default.v":

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Fri Dec 16 16:56:08 2005 Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synp

# # # # Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc. # Copyright 1994-2004 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Fri D

/* r128_state.c -- State support for r128 -*- linux-c -*- * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com * * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights R

/* r128_state.c -- State support for r128 -*- linux-c -*- * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com * * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights R

function state_trans_matrix = state_trans_build(state_number,L,state_all) %-------------------------------------------------------------------------- %构造状态转移矩阵 state_trans_matrix = zeros(state_numb

function state_all = state_all_build(L,phase_state) %-------------------------------------------------------------------------- %构造所有状态 state_number = 2^L*4; %计算状态数 for i = 1:L