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State Machine 的代码
state2_default.srs
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri D
state2_default.v
//Add a default state to make it more safe
module state2_default ( nrst,clk,
i1,i2,
o1,o2,
err
);
input nrst,cl
r128_state.c
/* r128_state.c -- State support for r128 -*- linux-c -*-
* Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
*
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
* All Rights R
cv_spec_state.hh
/*
* Copyright (c) 2001, 2002, 2003, 2004, 2005
* The Regents of The University of Michigan
* All Rights Reserved
*
* This code is part of the M5 simulator, developed by Nathan Binkert,
* Erik H
cv_spec_state.cc
/*
* Copyright (c) 2001, 2002, 2003, 2004, 2005
* The Regents of The University of Michigan
* All Rights Reserved
*
* This code is part of the M5 simulator, developed by Nathan Binkert,
* Erik H
rdopt_coding_state.h
/**********************************************************************
* Software Copyright Licensing Disclaimer
*
* This software module was originally developed by contributors to the
* cou
rdopt_coding_state.c
/**********************************************************************
* Software Copyright Licensing Disclaimer
*
* This software module was originally developed by contributors to the
* cou