代码搜索结果

class C4State { private static boolean[][][] map; private int[][] score = new int[2][winPlaces]; public static final int winPlaces = 69, maxPieces = 42, Empty = 2; privat

/*! *************************************************************************** * \file * rdopt_coding_state.h * * \author * Heiko Schwarz * * \date * 17. April 2001 *

/*! *************************************************************************** * \file rdopt_coding_state.c * * \brief * Storing/restoring coding state for * Rate-Distortion optim

/* r128_state.c -- State support for r128 -*- linux-c -*- * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com * * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights R

/* r128_state.c -- State support for r128 -*- linux-c -*- * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com * * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights R

function [s]=generate_starting_state() global Map_Data Speed_Vector_Indexes Pos_Vector_Indexes Finish_Data % generate_starting_state : generates a random state within the list of [x y 0 0] states %

function [s]=convert_values_to_state(x,y,vx,vy) global VMAX Map_Data Pos_Vector_Indexes Speed_Vector_Indexes % convert_values_to_state: Converts a [x y vx vy] representation to the %

#### START OF AREA REPORT #####[ Part: EP1S10FC780-5 (Altera) ---------------------------------------------------------------------- ######## Utilization report for Top level view: state

log_puts {@N|Using encoding styles selected by FSM Explorer.} log_puts {Data created on Fri Dec 16 18:27:37 2005} define_attribute {work.state2.verilog|i:CS[3:0]} syn_encoding {sequential}

source "C:/eda/synplicity/fpga_81/lib/altera/quartus_cons.tcl" syn_create_and_open_prj state2 source $::quartus(binpath)/prj_asd_import.tcl syn_create_and_open_csf state2 syn_handle_cons state2 s