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State Machine 的代码
state_m2.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
state_m2.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
state_m2.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
[ProjectWorkspace.Frames.ChildFrames.Document-0]
state_m2.vhd
--4.9 状态机的优化设计
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY state_m2 IS
PORT(
clk : in std_logic;
reset : in s
state_m2.pss
|
c230ba4e6f62c2694d4ce6d4ba1c6045
state_m2.hif
Version 6.1 Build 201 11/27/2006 SJ Full Version
39
2138
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--
state_m2.pin
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
state_m2.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY state_m2 IS
PORT(clk, reset, nw : in std_logic;
sel: out std_logic_vector(1 down