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#Begin clock constraint define_clock -name {b:state2|clk} -period 2.746 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 1.373 -route 0.000 #End clock constraint

f "noname"; #file 0 f "noname"; #file 1 f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2 f "c:\prj\fsm_abc\state_default\state2_default.v"; #file 3 VNAME 'LUCENT.VLO.PRIM'; # view id 0 VNAM

@P: Worst Slack : -0.484 @P: state2_default|clk - Estimated Frequency : 309.6 MHz @P: state2_default|clk - Requested Frequency : 364.2 MHz @P: state2_default|clk - Estimated Period : 3.230 @P:

# # Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R. # # Period Constraints FREQUENCY PORT "clk" 364.2 MHz; # Output Constraints # Input Constraints BLOCK ASYNCPATHS;

(edif state2_default (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2005 12 16 16 56 10) (author "Synplicity, Inc.")

Selecting top level module state2_default @N:"C:\prj\FSM_abc\state_default\state2_default.v":2:7:2:20|Synthesizing module state2_default @N: CL201 :"C:\prj\FSM_abc\state_default\state2_default.v":

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Fri Dec 16 16:56:08 2005 Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synp

# # # # Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc. # Copyright 1994-2004 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Fri D

//Add a default state to make it more safe module state2_default ( nrst,clk, i1,i2, o1,o2, err ); input nrst,cl