代码搜索结果

/*! *************************************************************************** * \file rdopt_coding_state.c * * \brief * Storing/restoring coding state for * Rate-Distortion optim

/* *********************************************************************** * COPYRIGHT AND WARRANTY INFORMATION * * Copyright 2001, International Telecommunications Union, Geneva * * DISCLAIMER OF WAR

/* *********************************************************************** * COPYRIGHT AND WARRANTY INFORMATION * * Copyright 2001, International Telecommunications Union, Geneva * * DISCLAIMER OF WAR

#### START OF AREA REPORT #####[ Part: EP1S10FC780-5 (Altera) ---------------------------------------------------------------------- ######## Utilization report for Top level view: state

log_puts {@N|Using encoding styles selected by FSM Explorer.} log_puts {Data created on Fri Dec 16 18:27:37 2005} define_attribute {work.state2.verilog|i:CS[3:0]} syn_encoding {sequential}

source "C:/eda/synplicity/fpga_81/lib/altera/quartus_cons.tcl" syn_create_and_open_prj state2 source $::quartus(binpath)/prj_asd_import.tcl syn_create_and_open_csf state2 syn_handle_cons state2 s

set_global_assignment -name ROOT "|state2" -remove set_global_assignment -name FAMILY -remove set_global_assignment -section_id clk_setting -name DUTY_CYCLE "50.00" -remove set_instance_assignme

#Begin clock constraint define_clock -name {b:state2|clk} -period 1.000 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 0.500 -route 0.000 #End clock constraint

#Begin clock constraint define_clock -name {b:state1|clk} -period 1.961 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 0.981 -route 0.000 #End clock constraint